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Quad, IEEE 802.3at/af PSE Controller
for Power-over-Ethernet
START and STOP Conditions
Both SCL and SDA remain high when the interface is not
busy. A master signals the beginning of a transmission
with a START (S) condition by transitioning SDA from
high to low while SCL is high. When the master finishes
communicating with the slave, the master issues a STOP
(P) condition by transitioning SDA from low to high while
SCL is high. The STOP condition frees the bus for anoth-
er transmission (see Figure 6).
Bit Transfer
Each clock pulse transfers one data bit (Figure 7). The
data on SDA must remain stable while SCL is high.
SDA/
SDAIN
Acknowledge
The acknowledge bit is a clocked 9th bit (Figure 8) that
the recipient uses to handshake receipt of each byte of
data. Thus, each byte transferred effectively requires
9 bits. The master generates the 9th clock pulse, and
the recipient pulls down SDA during the acknowledge
clock pulse, so the SDA line is stable low during the high
period of the clock pulse. When the master transmits to
the MAX5980, the device generates the acknowledge
bit. When the device transmits to the master, the master
generates the acknowledge bit.
SDA/SDAIN
SCL
S
P
SCL
START
STOP
DATA LINE STABLE;
DATA VALID
CHANGE OF
DATA ALLOWED
Figure 6. START and STOP Conditions
START CONDITION
Figure 7. Bit Transfer
CLOCK PULSE FOR ACKNOWLEDGMENT
SCL
1
2
8
9
SDA/SDAIN
BY TRANSMITTER
S
SDA/SDAOUT
BY RECEIVER
Figure 8. Acknowledge
23
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